1. Field of the Invention
The invention generally relates to computer bus systems and in particular to a bridge or interface element for interconnecting a host computer bus with a personal computer interface (PCI) bus.
2. Brief Description of Related Art
PCI bus systems are becoming increasingly popular for use within personal computers, particularly, personal computers configured as file servers. A PCI bus is a high performance, high bandwidth bus configured in accordance with protocols established by the PCI Special Interest Group. A PCI bus is operated in either a 32-bit single address mode, a 32-bit dual address mode, a 64-bit single address mode or a 64-bit dual address mode.
In the single address 32-bit mode, a single 32-bit address is employed in connection with 64-bit data packets. Figure 1a illustrates the arrangement of address and data signals, and related commands and byte enable signals, for a write transaction in the 32-bit single address mode. In a first clock cycle, the PCI bus transmits a 32-bit address and corresponding command bits. In the second clock cycle, the PCI bus transmits a first 32 bits of a 64-bit data packet along with corresponding byte enable bits. If there are more than 32 bits, then during a third clock cycle, the PCI bus transmits the remaining 32 bits of the 64-bit data packet and corresponding byte enable bits. Thus, one transmission of data and a corresponding 32-bit address requires three clock cycles. Although referred to as a 32-bit bus, the bus actually transmits more than 32 bits on each clock cycle, i.e., byte enable and command signals are transmitted simultaneously with 32 bits of address or data.
Figure 1b illustrates the dual mode 32-bit PCI bus protocol. During a first pair of clock cycles, the top and bottom 32 bits of a 64-bit address are transmitted along with corresponding commands bits. During a second pair of clock cycles, the top and bottom 32 bits of a 64-bit data packet are transmitted along with corresponding byte enable bits. Accordingly, four clock cycles are required to transmit 64 bits of data and a corresponding 64-bit address. Three clock cycles are required for 64 bits address and 32 bits of data. As with the single address 32-bit mode, the dual address 32-bit mode actually provides more than 32 bits during each clock cycle.
Figure 1c illustrates a dual address 64-bit PCI mode. During a first dock cycle, all 64 bits of a 64-bit address are transmitted along with corresponding command bits. During a second clock cycle, the upper 32 address bits are repeated on-the lower address/data lanes. This is provided so that 32-bit devices can work with 64-bit devices. During a third clock cycle, all 64 bits of a 64-bit data packet are transmitted along with corresponding byte enable bits. As such, only three clock cycles are required to transmit 64 bits and a corresponding 64-bit address. 64 bits of additional data is transmitted on each clock. Hence, the dual address 64-bit PCI mode has twice the bandwidth of the dual 32-bit PCI mode.
Figure 1d illustrates the single address 64-bit PCI mode. During a first clock cycle, 32 address bits are transmitted along with command bits. During a second clock cycle, 64 data bits are transmitted along byte enable bits. As such, only two clock cycles are required to transmit 64 bits of data and a corresponding 32-bit address. In all four PCI modes, actual transmission of data may be performed in accordance with burst processing techniques to facilitate high speed transference of data.
In a typical computer system employing a PCI bus, a PCI-to-host interconnection bridge is provided between the PCI bus and a host bus of the computer system. Host computer buses are not typically configured in accordance with PCI protocols. The bridge is provided, in part, to facilitate conversion of data from the PCI format to a format employed by the host bus. Many PCI-to-host bridges are configured to accommodate only a 32-bit PCI bus. Others are configured to accommodate either only a 64-bit PCI bus or only a 32-bit PCI bus. Accordingly, to accommodate more than one PCI bus requires additional PCI-to-host bridges. For many computer systems, particularly file server computer systems, numerous PCI buses must be accommodated. The conventional arrangement, wherein one bridge is required for each PCI bus, offers little flexibility. Moreover, many state of the art host buses are highly sensitive to the number of components, such as bridges, connected to the bus. With such buses the maximum permissible clock rate is often inversely proportional to the number of components connected to the host bus. Accordingly, the connection of additional bridges to the host bus results in a lowering of the maximum permissible clock rate, thereby lowering the overall performance of the system. Such is a particular problem with state of the art computer systems which may include as many as four host processors connected to the host bus along with one or more memory controllers or other components. Within such systems, the connection of an additional PCI bridge may lower the maximum permissible bus rate to a level which significantly hinders the performance of the overall computer system.
Accordingly, it would be desirable to provide an arrangement for interconnecting PCI buses to a host bus which allows further flexibility in connecting 32-bit and 64-bit PCI buses and which does not necessarily require connection of additional loads to the host bus. It is to these ends that aspects of the invention are drawn.